The present Invention relates to a method for manufacturing a low voltage driven field emitter array, and more particularly, to a method for manufacturing a low voltage driven field emitter array with gate holes of smaller diameters than those defined by photomask.
Field emission display (FED), as a kind of flat panel displays, has been object of active developments for reseachers and laboratories over the world. A field emitter array (FEA) functions with its cathode and gate and the development of LOW voltage driven FEA holds the key to success or failure of FED.
Emission current of a field emitter increases as the electric field applied to its cathode tip, that is, the field emitting tip, by its gate electrode to which a relatively positive(+) voltage is applied, has increased. Because the strength of the electric field applied to the cathode tip is in inverse proportion to the size of the gated field emitter [N. E. McGruer and Z. Huang. IVMC '93 Technical Digest, P. 135 (1993)], the smaller the size of the device is, the lower its driven voltage gets.
Further, as the size of the emitter tips as the source of emission of electrons gets smaller, the packing density of the field emitters can be increased, resulting in the lowered driving voltage of the FEA.
Therefore, studies for reducing the size of field emitter have long been under way, but there exist some limitations on reducing the diameter of the gate hole by photomask works, including one as used in so-called Spindt process.
The essential part of the Spindt process is to form a pattern of gate holes with a diameter of about 1 .mu.m and photomask aligner, electron beam lithography, or ion beam lithography equipment is used to form the gate hole pattern on the photoresist layer.
When using the photomask aligner, it is possible to form the number of gate hole patterns over the whole substrate at a time, but hard to obtain the pattern of the gate holes with the diameter of less than 1 .mu.m.
On the contrary, when using electron lithography or ion beam lithography equipment, it is possible to make gate holes with the diameter of less than 1 .mu.m, but improper to employ them for mass production of FED panels, since the electron beam and the ion beam scan the gate hole patterns one by one to form all gate hole pattern over the whole substrate, requiring a long time period.
As a solution to the above problems, a method for reducing the size of gate holes by using side-wall formation technique was disclosed [D. Stephani, D. Peters, W. Bartsch, C. A. Spindt, and C. E. Holland, IVMC '92, Program and Abstratcts, P. 8-4(1992)]. In this method, the first step is to form cathode, insulated layer and gate sequentially and to deposit the first sacrificial layer on them. Then, gate holes with the diameter of about 1 .mu.m are formed by using the process of photolithography and the second sacrificial layer is deposited and dry-etched, reducing the diameter of the holes in the second sacrificial layer to about 0.4 .mu.m and thus the gate electrodes are formed through etching process in which the second sacrificial layer is used as the etching mask.